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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
January 1999
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
General Description
The NMC27C64 is a 64K UV erasable, electrically reprogrammable and one-time programmable (OTP) CMOS EPROM ideally suited for applications where fast turnaround, pattern experimentation and low power consumption are important requirements. The NMC27C64 is designed to operate with a single +5V power supply with 10% tolerance. The CMOS design allows the part to operate over extended and military temperature ranges. The NMC27C64Q is packaged in a 28-pin dual-in-line package with a quartz window. The quartz window allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written electrically into the device by following the programming procedure. The NMC27C64N is packaged in a 28-pin dual-in-line plastic molded package without a transparent lid. This part is ideally suited for high volume production applications where cost is an important factor and programming only needs to be done once. This family of EPROMs are fabricated with Fairchild's proprietary, time proven CMOS double-poly silicon gate technology which combines high performance and high density with low power consumption and excellent reliability.
Features
High performance CMOS -- 150 ns access time JEDEC standard pin configuration -- 28-pin Plastic DIP package -- 28-pin CERDIP package Drop-in replacement for 27C64 or 2764 Manufacturers identification code
Block Diagram
VCC GND VPP Data Outputs O0 - O7
OE PGM CE
Output Enable, Chip Enable, and Program Logic
Output Buffers
..
Y Decoder
A0 - A12 Address Inputs
65,536-Bit Cell Matrix
.......
X Decoder
DS008634-1
(c) 1998 Fairchild Semiconductor Corporation NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Connection Diagram
27C512 27C256 27C128 27C32 27C16 27512 27256 27128 2732 2716
NMC27C64
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
27C16 2716
27C32 27C128 27C256 2732 27128 27256
27C512 27512
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
Note:
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
VCC PGM VCC NC VCC A8 A8 A8 A9 A9 A9 VPP A11 A11 OE OE/VPP OE A10 A10 A10 CE CE/PGM CE O7 O7 O7 O6 O6 O6 O5 O5 O5 O4 O4 O4 O3 O3 O3
VCC VCC VCC PGM A14 A14 A13 A13 A13 A8 A8 A8 A9 A9 A9 A11 A11 A11 OE OE/VPP OE A10 A10 A10 CE CE/PGM CE O7 O7 O7 O6 O6 O6 O5 O5 O5 O4 O4 O4 O3 O3 O3
DS008634-2
Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C64 pins.
Pin Names
A0-A12 CE OE O0 -O7 PGM NC VPP V CC GND Addresses Chip Enable Output Enable Outputs Program No Connect Programming Voltage Power Supply Ground
Commercial Temperature Range VCC = 5V 10%
Parameter/Order Number
NMC27C64Q, N 150 NMC27C64Q, N 200
Access Time (ns)
150 200
Extended Temp Range (-40 C to +85 C) VCC = 5V 10%
Parameter/Order Number
NMC27C64QE, NE200
Access Time (ns)
200
2
NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Absolute Maximum Ratings (Note 1)
Temperature Under Bias Storage Temperature All Input Voltages except A9 with Respect to Ground (Note 10) -55 C to +125 C -65 C to +150 C +6.5V to -0.6V
Power Dissipation Lead Temperature (Soldering, 10 sec.) ESD Rating (Mil Spec 883C, Method 3015.2)
1.0W 300 C
2000V
All Output Voltages with Respect to Ground (Note 10)VCC +1.0V to GND -0.6V V PP Supply Voltage and A9 with Respect to Ground During Programming V CC Supply Voltage with Respect to Ground
Operating Conditions (Note 7)
Temperature Range NMC27C64Q 150, 200 NMC27C64N 150, 200 NMC27C64QE 200 NMC27C64NE 200 VCC Power Supply 0 C to +70 C -40 C to +85 C +5V 10%
+14.0V to -0.6V +7.0V to -0.6V
READ OPERATION DC Electrical Characteristics
Symbol
ILI ILO ICC1 (Note 9) ICC2 (Note 9) ICCSB1 ICCSB2 IPP VIL VIH V OL1 VOH1 V OL2 VOH2
Parameter
Input Load Current Output Leakage Current V CC Current (Active) TTL Inputs V CC Current (Active) CMOS Inputs V CC Current (Standby) TTL Inputs V CC Current (Standby) CMOS Inputs VPP Load Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage
Conditions
VIN = V CC or GND VOUT = VCC or GND, CE = V IH CE = VIL ,f=5 MHz Inputs = V IH or V IL, I/O = 0 mA CE = GND, f = 5 MHz Inputs = VCC or GND, I/O = 0 mA CE = VIH CE = VCC VPP = V CC
Min
Typ
Max
10 10
Units
A A mA mA mA A
5 3 0.1 0.5 10 -0.1 2.0
20 10 1 100 A 0.8 VCC +1 0.45
V V V V
IOL = 2.1 mA IOH = -400 A IOL = 0 A IOH = 0 A VCC - 0.1 2.4
0.1
V V
AC Electrical Characteristics
NMC27C64 Symbol tACC tCE tOE tDF tCF tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float CE High to Output Float Output Hold from Addresses, CE or OE , Whichever Occurred First Conditions Min CE = OE = VIL PGM = VIH OE = VIL, PGM = VIH CE = VIL, PGM = V IH CE = VIL, PGM = V IH OE = VIL, PGM = VIH CE = OE = VIL PGM = VIH 0 0 0 150 Max 150 150 60 60 60 0 0 0 200, E200 Min Max 200 200 60 60 60 Units ns ns ns ns ns ns
3
NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Capacitance TA = +25C, f = 1 MHz (Note 2) NMC27C64Q
Symbol
CIN COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VIN = 0V VOUT = 0V
Typ
6 9
Max
8 12
Units
pF pF
Capacitance TA = +25C, f = 1 MHz (Note 2) NMC27C64N
Symbol
CIN COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VIN = 0V VOUT = 0V
Typ
5 8
Max
10 10
Units
pF pF
AC Test Conditions
Output Load 1 TTL Gate and C L = 100 pF (Note 8) 5 ns 0.45V to 2.4V 0.8V and 2V 0.8V and 2V Input Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level Inputs Outputs
AC Waveforms (Note 6) (Note 9)
ADDRESS
2V 0.8V
Address Valid
CE
2V 0.8V
t CF t CE t OE
(Note 3) (Notes 4, 5)
OE
2V 0.8V
t DF
(Notes 4, 5)
Valid Output
OUTPUT
2V 0.8V
Hi-Z t ACC
(Note 3)
Hi-Z t OH
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE (R) , the measured VOH1 (DC) 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 A. CL: 100 pF includes fixture capacitance. Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
4
NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Programming Characteristics (Note 11) (Note 12) (Note 13) (Note 14)
Symbol
tAS tOES tCES tDS tVPS tVCS tAH tDH tDF tPW tOE IPP ICC TA VCC VPP tFR VIL VIH tIN tOUT
Parameter
Address Setup Time OE Setup Time CE Setup Time Data Setup Time V PP Setup Time V CC Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay Program Pulse Width Data Valid from OE V PP Supply Current During Programming Pulse V CC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Conditions
Min
2 2 2 2 2 2 0 2
Typ
Max
Units
s s s s s s s s
CE = V IL
0 0.45 0.5
130 0.55 150 30 10
ns ms ns mA mA C V V ns
CE = V IL CE = V IL PGM = VIL
20 5.75 12.2 5
25 6.0 13.0
30 6.25 13.3
0.0 2.4 0.8 0.8 4.0 1.5 1.5
0.45
V V
2.0 2.0
V V
5
NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Programming Waveforms (Note 13)
Program ADDRESS
2V 0.8V
Program Verify
Address N
t AS DATA
2V 0.8V
Data In Stable Add N
t AH Hi-Z
Data Out Valid Add N
t DS
t DH
t DF
6.0V
VCC
13.0V
tVCS
VPP
t VPS
CE
0.8V
t CES
2V 0.8V
PGM
t PW
2V
t OES
t OE
OE
0.8V
Note 11: Fairchild's standard product warranty applies to devices programmed to specifications described herein. Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 F capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Note 14: Programming and program verify are tested with the interactive Program Algorithm, at typical power supply voltages and timings.
6
NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Fast Programming Algorithm Flow Chart
Start
ADDR = First Location
VCC = 6.25 V VPP = 12.75V
X=0
Program one 100 s Pulse
Increment X
X = 20 ?
Yes
No
Fail
Verify Byte Pass
Verify Byte
Fail
Device Failed
Pass
Increment ADDR
No
Last Address
Yes
1st VCC = VPP =5.5V 2nd VCC = VPP =4.5V
Fail
Device Failed
Pass Device Passed
FIGURE 1.
7
NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C64 are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are V CC and VPP . The VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6V during the three programming modes, and at 5V in the other three modes.
To most efficiently use these two control lines, it is recomended that CE (pin 20) be decoded and used as the primary device selecting function, while OE (pin 22) be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (VPP ) will damage the NMC27C64. Initially, all bits of the NMC27C64 are in the "1" state. Data is introduced by selectively programming "0s" into the desired bit locations. Although only "0s" will be programmed, both "1s" and "0s" can be presented in the data word. A "0" cannot be changed to a "1" once the bit has been programmed. The NMC27C64 is in the programming mode when the VPP power supply is at 12.75V and OE is at V IH. It is required that at least a 0.1 F capacitor be placed across V PP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. For programming, CE should be kept TTL low at all times while V PP is kept at 12.75V. When the address and data are stable, an active low, TTL program pulse is applied to the PGM input. A program pulse must be applied at each address location to be programmed. The NMC27C64 is programmed with the Fast Programming Algorithm shown in Figure 1. Each address is programmed with a series of 100 s pulses until it verfies good, up to a maximum of 25 pulses. Most memory cells will program with a single 100 s pulse. The NMC27C64 must not be programmed with a DC signal applied to the PGM input. Programming multiple NMC27C64s in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the paralleled NMC27C64s may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled NMC27C64s. If an application requires erasing and reprogramming, the NMC27C64Q UV erasable PROM in a windowed package should be used.
Read Mode
The NMC27C64 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. The programming pin (PGM) should be at VIH except during programming. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE , assuming that CE has been low and addresses have been stable for at least tACC - tOE. The sense amps are clocked for fast access time. V CC should therefore be maintained at operating voltage during read and verify. If V CC temporarily drops below the spec. voltage (but not to ground) an address transition must be performed after the drop to insure proper output data.
Standby Mode
The NMC27C64 has a standby mode which reduces the active power dissipation by 99%, from 55 mW to 0.55 mW. The NMC27C64 is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.
Output OR-Tying
Because NMC27C64s are usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur.
TABLE 1. Mode Selection Pins Mode
Read Standby Output Disable Program Program Verify Program Inhibit
CE (20)
VIL V IH Don't Care V IL VIL V IH
OE (22)
V IL Don't Care V IH VIH V IL Don't Care
PGM (27)
VIH Don't Care VIH
VPP (1)
5V 5V 5V 13V
VCC (28)
5V 5V 5V 6V 6V 6V
Outputs (11-13, 15-19)
DOUT Hi-Z Hi-Z DIN D OUT Hi-Z
VIH Don't Care
13V 13V
8
NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Functional Description (Continued)
Program Inhibit
Programming multiple NMC27C64s in parallel with different data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel NMC27C64 may be common. A TTL low level program pulse applied to an NMC27C64's PGM input with CE at V IL and VPP at 13.0V will program that NMC27C64. A TTL high level CE input inhibits the other NMC27C64s from being programmed.
After programming, opaque labels should be placed over the NMC27C64's window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. The recommended erasure procedure for the NMC27C64 is exposure to short wave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2 . The NMC27C64 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. The erasure time increases as the square of the distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.
Program Verify
A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 13.0V. VPP must be at V CC, except during programming and program verify.
MANUFACTURER'S IDENTIFICATION CODE
The NMC27C64 has a manufacturer's identification code to aid in programming. The code, shown in Table 2, is two bytes wide and is stored in a ROM configuration on the chip. It identifies the manufacturer and the device type. The code for the NMC27C64 is "8FC2", where "8F" designates that it is made by Fairchild Semiconductor, and "C2" designates a 64k part. The code is accessed by applying 12V 0.5V to address pin A9. Addresses A1-A8, A10-A12, CE, and OE are held at VIL. Address A0 is held at V IL for the manufacturer's code, and at V IH for the device code. The code is read out on the 8 data pins. Proper code access is only guaranteed at 25 C 5 C. The primary purpose of the manufacturer's identification code is automatic programming control. When the device is inserted in a EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer--the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated V CC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between V CC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 F bulk electrolytic capacitor should be used between V CC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C64 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A - 4000A range.
TABLE 2. Manufacturer's Identification Code Pins
Manufacturer Code Device Code
A0 (10)
V IL VIH
O7 (19)
1 1
O6 (18)
0 1
O5 (17)
0 0
O4 (16)
0 0
O3 (15)
1 0
O2 (13)
1 0
O1 (12)
1 1
O0 (11)
1 0
Hex Data
8F C2
9
NMC27C64 Rev. C
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NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.260 MAX (32.00) 24 R 0.025 (0.64) 13
0.514 - 0.526 (13.06 - 13.21)
1 R 0.030-0.055 TYP (0.76 - 1.4) 0.270 - 0.290 (6.88 - 7.39) UV WINDOW
12
0.050-0.060 TYP (1.27 - 1.53) Glass Sealant 0.225 MAX TYP (5.73) 0.125 MIN (3.18) TYP
0.180 (4.59) MAX
0.10 (2.5) MAX
0.590-0.620 (15.03 - 15.79)
0.020 -0.070 (0.51 - 1.78) TYP 0.090-0.110 (2.29 - 2.80) TYP 0.015-0.021 (0.38 - 0.53) TYP
90 - 100 TYP
0.060-0.100 (1.53 - 2.55) TYP
0.008-0.015 (0.20 - 0.38) TYP +0.025 (0.64) -0.060 (-1.523)
0.685 (17.40)
Dual-In-Line Package (Q) Order Number NMC27C64Q Package Number J28AQ
28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.030 Max (0.762) 0.600 - 0.620 (15.24 - 15.75) 0.062 RAD (1.575)
0.510 0.005 (12.95 0.127)
95
5 0.580 (14.73) 0.008-0.015 (0.229-0.381) Pin #1 IDENT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.393 - 1.420 (35.38 - 36.07) 0.050 (1.270) Typ 0.125-0.165 (3.175-4.191) 0.20 Min (0.508)
+0.025 0.625 -0.015
(15.88 +0.635 -0.381
0.053 - 0.069 (1.346 - 1.753)
0.050 0.015 (1.270 0.381)
0.108 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076)
88 94 Typ
0.125-0.145 (3.175-3.583)
Dual-In-Line Package (N) Order Number NMC27C64N Package Number N28B
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, T simshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
NMC27C64 Rev. C
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